FIG. 48 is a block diagram showing an example of a configuration of a SONET (SDH transmission network). A SONET 100 shown in FIG. 48 has a multi ring configuration wherein, for example, a 10 G ring 101 which handles a data transmission rate of the OC-192 level (approximately 10 Gbps), and an OC (Optical Carrier)-12 loop ring network 102 which handles a data transmission rate of the OC-12 level (approximately 622 Mbps) and an OC-3 loop ring network 103 which handles a data transmission rate of the OC-3 level (approximately 155 Mbps) are connected to each other through SONET transmission apparatus 111, 112, 121 and 122 which serve as gateways. It is to be noted that the transmission apparatus 121 accommodates also a ring network 104 of a data transmission rate of the DS3 (Digital Signal level 3) or STS-1 level (approximately 51 Mbps).
Therefore, at least the SONET transmission apparatus 111, 112, 121 and 122 which serve as gateways require a function of supporting processing for a plurality of signals of different data transmission rates, a cross connect (TSA: Time Slot Assignment) function and so forth. If attention is paid, for example, to the SONET transmission apparatus 121 (which may be hereinafter referred to merely as “transmission apparatus”), it is necessary that it can perform signal processing of the different levels including the OC-12, OC-3, DS-3 and STS-1 levels and that it can cross connect receive signals to desired ones of the ring networks 100 to 104.
In order to support such functions as described above, the transmission apparatus 121 includes, if attention is paid to a configuration of essential part of the same, for example, as shown in FIG. 49, a suitable number of higher level group interface units 201 ready for the OC-12/OC-3 levels and a suitable number of lower level group interface units 202 ready for the DS3/STS-1 levels individually corresponding to the numbers of transmission/reception destinations, and an STS cross connect unit 203 which accommodates the interface units (hereinafter referred to as IF boards) 201 and 202 and performs cross connect processing in a unit of a channel (here, STS-1). It is to be noted that reference numeral 204 denotes a synchronization card (SYNC) for supplying an intra-apparatus (unit) reference clock to the units 201 to 203.
Each of the IF boards 201 and 202 includes a channel (CH) interface section 210 which in turn includes a demultiplex processing section (DMUX) 211, a P/S (parallel/serial) conversion circuit 212, an S/P (serial/parallel) conversion circuit 213, a PLL circuit 214 and a multiplex processing section (MUX) 215. The STS cross connect unit 203 includes an STS-TSA section 230 which in turn includes an S/P conversion circuit 231, a pointer processing circuit 232, a cross connect section 233, a PLL circuit 234 and a P/S conversion circuit 235.
It is to be noted that, although not shown for simplified illustration in FIG. 49, the STS-TSA section 230 actually includes a number of S/P conversion circuits 231, pointer processing circuits 232, P/S conversion circuits, PLL circuits 234 and P/S conversion circuits 235 equal to the number of the accommodated IF boards 201 and 202 in order to perform signal processing for each of the IF boards 201 and 202.
In each of the IF boards 201 and 202, the DMUX 211 demultiplexes (extracts) a main signal (frame) in frame synchronism with a receive signal, and the demultiplexed main signal is outputted to the P/S conversion circuit 212 together with a frame pulse (FP) representative of the top position of the main signal and a clock signal (CK). It is to be noted that the DMUX 211 additionally has such a pointer processing function well-known in the art as hereinafter described.
The P/S conversion circuit 212 performs S/P conversion of the main signal from the DMUX 211 in accordance with the frame pulse and the clock described above in order to pass the main signal at a high rate to the STS cross connect unit 203. The main signal after the S/P conversion is outputted as N (N is an integer equal to or greater than 2) parallel data to the STS cross connect unit 203 together with the frame pulse and the clock described above through a back plane interface 205.
The S/P conversion circuit 213 performs S/P conversion of the main signal (N parallel data) after the cross connect processing transferred thereto at a high rate from the STS cross connect unit 203 through the back plane interface 205 in accordance with the frame pulse representative of the top position of the main signal and the clock in order to process the main signal at a low rate. The PLL circuit 214 produces an intra-unit reference master clock synchronized with the intra-unit reference clock signal supplied thereto from the synchronization card 204.
The MUX 215 performs pointer processing and processing (MUX processing) such as insertion of an overhead and so forth for the main signal from the S/P conversion circuit 213 described above in accordance with the intra-unit reference master clock supplied thereto from the PLL circuit 214 to produce a predetermined signal (frame) of the OC-12/OC-3 or the DS3/STS-1 and signals the predetermined signal to the network side.
On the other hand, each of the S/P conversion circuits 231 in the STS-TSA section 230 performs S/P conversion of the main signal sent thereto at a high rate from a corresponding one of the IF boards 201 or 202 through the back plane interface 205 in accordance with the frame pulse and the clock sent thereto together with the main signal in order to process the main signal at a low rate. The pointer processing circuit 232 performs well-known pointer processing such as NDF (New Data Flag) enable detection and pointer value detection for the main signal after the S/P conversion by the S/P conversion circuit 231 in accordance with the intra-unit reference master clock supplied thereto from the PLL circuit 234 to absorb any displacement of the frame top position of the main signal from the corresponding one of the IF boards 201 or 202 so that such frame top positions are adjusted to one another.
The cross connect section 233 performs TSA in a unit of a channel (STS-1) for the main signals, whose frame top positions have been adjusted by the pointer processing circuits 232 in this manner, in accordance with the intra-unit reference master clock supplied thereto from the PLL circuit 234 to perform cross connection in a unit of channel of the receive signals. It is to be noted that setting of the cross connect (including through-setting) is performed from the outside by a system CPU (microcomputer) not shown or the like.
The PLL circuit 234 is similar to the PLL circuit 214 of the IF boards 201 and 202 and produces the intra-unit reference master clock described above synchronized with the intra-unit reference clock supplied thereto from the synchronization card 204. The P/S conversion circuit 235 performs P/S conversion of a main signal after the cross connect by the cross connect section 233 in accordance with the frame pulse representative of the top position of the main signal and the clock in order to transmit the main signal at a high rate to the pertaining IF board 201 or 202.
Operation of the SONET transmission apparatus 121 having such a configuration as described above is described below taking operation in a case wherein a signal (OC-12) on a network on the higher level group side (for example, the OC-12 loop ring network 102) accommodated in an IF board 201 is cross connected (dropped) to a network (for example, the ring network 104) of the lower level group (tributary) side accommodated in an IF board 202 as an example.
First, after a signal transmitted over the OC-12 loop ring network 102 is taken into an IF board 201, the DMUX 211 in the IF board 201 demultiplexes a main signal from the receive signal, and the P/S conversion circuit 212 performs P/S conversion of the main signal, whereafter the main signal, a frame pulse and a clock are outputted to the STS cross connect unit 203 through the back plane interface 205.
In the STS cross connect unit 203 (STS-TSA section 230), the main signal from the IF boards 201 is S/P converted by the S/P conversion circuit 231 and then inputted to the pointer processing circuit 232.
The pointer processing circuit 232 performs pointer processing for the main signal inputted thereto in accordance with an intra-unit reference master clock to adjust the frame top position of the main signal to the frame top positions of main signals from the other IF boards 201 or 202.
Consequently, the main signals from the IF boards 201 or 202 are inputted to the cross connect section 233 in such a condition that the frame top positions thereof are adjusted to one another (in a synchronized state). Then, the cross connect section 233 performs cross connect processing of the main signals with the frame top positions adjusted to one another in this manner in accordance with the intra-unit reference master clock and the cross connect setting set in advance.
More particularly, in this instance, TSA is performed so that the main signal received from the OC-12 loop ring network 102 may be outputted as a main signal to the ring network 104 to the pertaining P/S conversion circuit 235 (IF board 202).
The main signal after the cross connect is P/S converted by the pertaining P/S conversion circuit 235 and then outputted to the pertaining IF board 202 (which accommodates the ring network 104) through the back plane interface 205. In the IF board 202, the main signal is S/P converted by the S/P conversion circuit 213 and undergoes MUX processing by the MUX 215, whereafter it is signaled as a signal of the DS3 or STS-1 level to the ring network 104.
It is to be noted that, also when a main signal transmitted on the ring network 104 is to be cross connected to the OC-12 loop ring network 102 conversely to that described above or when different cross connection to that described above is to be performed, basically similar processing is performed although the IF boards 201 and 202 through which the main signal passes are different.
Now, the pointer processing circuit 232 described above is described in more detail.
FIG. 50 is a block diagram showing an example of a detailed configuration of the pointer processing circuit 232. The pointer processing circuit 232 shown in FIG. 50 includes a pointer value reception section 241, a J1 pulse production section 242, a memory section 243, a stuff control section 244, a pointer value calculation section 245, a pointer value insertion section 246, an NDF production section 247 and so forth.
The pointer value reception section 241 receives (detects), from within a receive signal (refer to FIG. 51: it is to be noted that the signal format shown in FIG. 51 indicates an STS-1 frame, and the signal format of the OC-12, the OC-3 or the like corresponds to a signal obtained by byte-multiplexing of 12 or 3 such STS-1 frames), a pointer value of lower order 10 bits of pointer bytes (H1 and H2 bytes: refer to FIG. 52) which are positioned in the fourth row of an overhead part 301.
The J1 pulse production section 242 recognizes a J1 byte position which is the top position of the main signal based on the pointer value detected by the pointer value reception section 241 and produces a J1 pulse (frame timing pulse of the main signal) at the timing of the position of the J1 byte. The memory section 243 temporarily stores the J1 pulse produced by the J1 pulse production section 242 and the receive data (main signal).
More particularly, the J1 pulse and the main signal described above are written into the memory section 243 in synchronism with a receive clock from the IF board 201 (202) and read out from the memory section 243 in synchronism with a transmission clock (the intra-unit reference master clock) under the stuff (INC/DEC) control of the stuff control section 244. Consequently, clock (timing) re-clocking processing of the receive data to the transmission clock (transmission frame timing) is performed.
The pointer value calculation section 245 supervises to detect which one of SPE (Synchronous Payload Envelope) addresses (refer to FIG. 53) as counted up to “782” from “0” where the position of the next byte to the H3 byte (stuff byte) is set as “0” coincides with the timing of the J1 pulse to determine a transmission pointer value. The pointer value insertion section 246 inserts the transmission pointer value determined by the pointer value calculation section 245 as a new pointer value into the transmission data (main signal) read out from the memory section 243.
The NDF production section 247 produces NDF bits (refer to FIG. 52) which are higher order 4 bits of the H1 byte described above and represent whether or not the pointer value exhibits a change. More particularly, in a normal state wherein normal data communication is proceeding, the NDF production section 247 produces a normal NDF value of “0110”, but if the pointer value exhibits a change because of connection of power supply, occurrence of a circuit fault [occurrence (detection) of an AIS (Alarm Indication Signal), detection of interruption of the clock or the like], release after occurrence of a memory slip or the like, then the NDF production section 247 produces an NDF enable of “1001”.
However, the NDF enable above is not produced (that is, invalidated) upon change of the pointer value when stuff control by the stuff control section 244 is performed. Further, the produced NDF bits are inserted into the transmission data by the pointer value insertion section 246.
In the pointer processing circuit 232 having the configuration described above, the J1 byte position which is the top position of the main signal is recognized by the pointer value reception section 241 based on the pointer value indicated by the pointer byte of the receive data, and a J1 pulse is produced by the J1 pulse production section 242 at the timing of the J1 byte position.
The receive data and the J1 pulse are written once into the memory section 243 in synchronism with a reception clock and then read out from the memory section 243 in synchronism with the transmission clock. At this time, if necessary, stuff control by the stuff control section 244 is performed. Then, the transmission pointer value is determined by the pointer value calculation section 245 from the timing of the J1 pulse thus read out, and the pointer value is inserted into the transmission data read out from the memory section 243 by 246. At this time, also the NDF bits produced by the NDF production section 247 are inserted.
Such processing as described above is executed for reception data from the IF boards 201 or 202 individually by the respective pointer processing circuits 232 to absorb displacements (bit delays) of the top positions of the receive data from the IF boards 201 or 202 caused by a difference in transmission path (used network), a processing delay by the IF board 201 or 202, a difference in physical distance (wiring line distance) between the IF board 201 or 202 and the STS cross connect unit 203 and other factors so that the frame timings of all of the receive data are brought into coincidence with one another thereby to allow cross connect processing by the cross connect section 233.
In this manner, in the SONET 100 or SDH transmission network, pointer processing is a technique used to re-clock (convert) the frame timing and the clock of data on a transmission line (network) (on the reception side) into a frame timing and a clock in the unit (transmission side) while suppressing a bit delay of receive data to the minimum.
It is to be noted that such pointer processing as described above is performed also by the DMUX 211 or the MUX 215 in the IF boards 201 and 202 in the transmission apparatus 121 shown in FIG. 49. This is intended to cause each of the IF boards 201 and 202 to absorb a displacement of the top position of the individual receive data which is caused by a difference in used network to some degree.
However, such a transmission apparatus 121 as described above is obliged to have a very great apparatus scale because a number of pointer processing circuits 232 corresponding to the number of IF boards 201 and 202 accommodated in the transmission apparatus 121 (the number corresponding to the number of channels to be processed) are required in order to perform timing re-clocking of receive data (main signal frames) from the IF boards 201 or 202.
Particularly, in order to allow a transmission apparatus (for example, 111) which can cope with a very high rate transmission network higher than the OC-192 level (approximately 10 Gbps) described above to cope various network schemes (applications) which handle the OC-12, OC-3, DS3, STS-1 and so forth, it is necessary to increase the number of IF boards (number of channels to be processed) which can be accommodated in the STS cross connect unit 203, and also additional pointer processing circuits 232 must be provided accordingly. This further increases the apparatus scale, and it is very difficult to implement such a transmission apparatus as described above using the LSI technique at present in terms of the mounting area and so forth.
Further, the transmission apparatus 121 described above has, since displacements of the frame top positions of main signals which are caused by a difference in processing delay by the IF boards 201 and 202 and physical distance (wiring line distance) to the IF boards 201 and 202 are absorbed by the pointer processing circuit 232, as shown in FIG. 49, a structure wherein each of the IF boards 201 and 202 may operate in accordance with an intra-unit reference master clock generated uniquely by its PLL circuit 214 based on the intra-unit reference clock, that is, may operate not in synchronism with the STS cross connect unit 203.
However, if the number of accommodated IF boards is increased in the structure just described, then displacements of the frame top positions of the main signals to the STS cross connect unit 203 appear further separately among the IF boards 201 and 202, resulting in increase of the fluctuation amounts (dispersion) of the “displacements” of the main signals.
Therefore, the memory section 243 of each of the STS-TSA sections 230 must have a memory capacity sufficient to absorb all of the “displacements” appearing separately among the IF boards 201 and 202 in this manner. Accordingly, the “timing re-clocking” which uses the pointer processing technique has a limitation to increase of the number of channels to be processed.
The present invention has been made in view of such a subject as described above, and it is an object of the present invention to provide an SDH transmission apparatus and a frame timing re-clocking method for an SDH transmission apparatus by which timing re-clocking of a main signal frame can be performed without using the pointer processing technique and increase of the apparatus scale can be suppressed to the minimum even if the number of channels to be processed increases.